Three point two. Replacement Algorithms
Three point four. Virtual Memory and Address Translation
Three point six. Addition and Subtraction of Signed Numbers
Three point eight. Summary
Three point ten. Self-Assessment Questions
Three point twelve. Reference
Three point one point one. Concept and Need for Cache Memory
Three point one point two. Cache Levels (L One, L Two, L Three) and Hierarchical Structure
Three point one point three. Cache Mapping Techniques: Direct, Associative, and Set-Associative
Three point one point four. Cache Line and Tag Structure
Three point two. Replacement Algorithms
Three point two point one. Need for Replacement Policies
Key Reasons for Replacement Policies:
Situations where replacement is triggered:
Three point two point two Least Recently Used Algorithm
Implementation Techniques:
Three point two point three First-In-First-Out Algorithm
Three point two point four Random and Optimal Replacement Policies
Optimal Replacement Policy Belady's Algorithm:
Additional Notes on Replacement Policy Design:
Three point three Performance Optimization in Cache
Three point three point one Cache Hit and Miss Ratio
Three point three point two Techniques to Improve Cache Performance
Replacement Policy Optimization:
Write Buffers and Coalescing:
Three point three point three Write Policies: Write-Through and Write-Back
Three point three point four Multilevel Caching Strategies
Multilevel Cache Hierarchy:
Benefits of Multilevel Caching:
Non-Inclusive/Non-Exclusive:
Three point four Virtual Memory and Address Translation
Three point four point one Concept of Virtual Memory
Benefits of Virtual Memory:
Three point four point two Paging and Segmentation
Combined Paging and Segmentation
Three point four point three Page Table Structure and Address Translation
Address Translation Process:
Page Table Entries (PTEs):
Translation Lookaside Buffer (TLB):
Three point four point four Page Fault Handling and Performance Issues
Steps in Page Fault Handling:
· Local vs Global Replacement:
· Minimizing Page Faults:
Three point five Logic Gates and Flip-Flops
Three point five point one Basic Logic Gates: AND, OR, NOT, NAND, NOR, XOR, XNOR
Three. NOT Gate (Inverter):
Six. XOR Gate (Exclusive OR):
Seven. XNOR Gate (Exclusive NOR):
Three point five point two Combinational Logic Circuits
Examples of Combinational Circuits:
· Demultiplexers (DEMUX):
Three point five point three Sequential Logic Circuits
· Asynchronous Sequential Circuits:
Three point five point four Flip-Flops: SR, JK, D, and T Types
One. SR Flip-Flop (Set-Reset):
Three. D Flip-Flop (Data or Delay Flip-Flop):
Four. T Flip-Flop (Toggle):
Three point five point five Applications of Flip-Flops in Digital Systems
Three point six Addition and Subtraction of Signed Numbers
Three point six point one Representation of Signed Numbers (Sign-Magnitude, one's and two's Complement)
One. Sign-Magnitude Representation:
Two. One's Complement Representation:
Three. Two's Complement Representation:
Three point six point two Binary Addition and Subtraction Rules
Binary Subtraction Rules:
Three point six point three Overflow Detection and Correction
Three point six point four Hardware Implementation of Arithmetic Operations
Subtraction Using 2's Complement:
Three point seven Fast Adder Designs Including Carry Look-Ahead Adder
Three point seven point one Limitations of Ripple Carry Adder
Three point seven point two Principle of Carry Look-Ahead Addition
Three point seven point three Design and Working of Carry Look-Ahead Adder
Carry Look-Ahead Generator:
Example: Four-bit Carry Look-Ahead Adder
Three point seven point four Comparison of Carry Look-Ahead Adder with Other Adder Designs
Three point nine Keywords
Three point ten. Self-Assessment Questions
Three point eleven. Case Study