Two point two. Assembly Language Instructions
Two point four. Subroutines
Two point six. Accessing I/O Devices
Two point one point one. Immediate Addressing Mode
Two point one point two. Direct Addressing Mode
Two point one point three. Indirect Addressing Mode
Two point one point four. Register Addressing Mode
Two point one point five. Indexed and Relative Addressing Modes
A. Indexed Addressing Mode
B. Relative Addressing Mode
Two point two. Assembly Language Instructions
Two point two point one. Structure of Assembly Language Instructions
Two point two point two. Data Transfer Instructions
Two point two point three Arithmetic and Logic Instruction
Two point two point four Branch and Control Instructions
Types of Branch Instructions:
Subroutine and Procedure Control:
Two point two point five Input/Output and Stack Instructions
A. Input/Output Instructions
Two point three Input and Output Operations
Two point three point one Program-Controlled I/O
Two point three point two Interrupt-Driven I/O
Two point three point three DMA-Controlled I/O (Direct Memory Access)
Two point three point four Synchronization and Data Transfer Methods
A. Synchronization Methods:
B. Data Transfer Methods:
Importance of Synchronization:
Two point four Subroutines
Two point four point one Concept of Subroutines and Procedures
Two point four point two Calling and Returning Mechanisms
Example (Assembly-style):
Two point four point three Parameter Passing Methods
Two point four point four Stack Implementation in Subroutines
Functions of Stack in Subroutines:
Advantages of Stack-Based Subroutines:
Two point five Instruction Encoding
Two point five point one Need for Instruction Encoding
Why Encoding is Necessary:
Goals of Instruction Encoding:
Two point five point two Opcode and Operand Fields
Common Fields in an Instruction:
Four. Miscellaneous Fields:
Example Format (Hypothetical sixteen-bit instruction):
Variable-Length Encoding:
Two point five point four Examples of Instruction Encoding Example One: Fixed-Length (RISC Style)
Example 2: Variable-Length (x86 Style)
Example 3: Stack-Based Architecture
Two point six. Accessing I/O Devices
Two point six point one. I/O Port Concept
Two point six point two. Memory-Mapped I/O vs. Isolated I/O
Isolated I/O, Port-Mapped I/O:
Two point six point three. I/O Device Control and Status Registers
Temporary holding places for input or output data.
Two point six point four. Handshaking and Data Transfer
Basic Handshaking Process:
Types of Data Transfer Techniques:
Two point seven. Interrupt Mechanism and Hardware
Two point seven point one. Interrupt Concepts and Types
Two point seven point two. Interrupt Cycle and Processing
Steps in Interrupt Cycle:
Two point seven point three. Interrupt Priority and Vectoring Interrupt Priority:
Two point seven point four. Hardware for Interrupt Handling
Two. Interrupt Controller:
Three. Interrupt Mask Register:
Five. Nested Interrupt Support:
Two point eight. Direct Memory Access, DMA
Two point eight point one. DMA Operation and Working Principle
Two point eight point two DMA Controller and Registers
Five. Request and Acknowledge Lines:
Two point eight point three Advantages of DMA over Interrupt I/O
Limitations of Interrupt I/O:
Two point eight point four DMA and System Performance
Performance Considerations:
Two point nine Standard I/O Interfaces
Two point nine point two Small Computer System Interface (SCSI)
Two point nine point three Universal Serial Bus (USB)
Two point ten Basic Memory Organization
Two point ten point one Memory Cell and Word Organization Memory Cell: The smallest unit of memory that stores one bit (zero or one).
Two point ten point two Random Access Memory (RAM)
Two point ten point three Read Only Memory (ROM)
Two point ten point four Memory Address Decoding
Two point eleven. Memory Hierarchy Principles
Two point eleven point one. Hierarchical Memory Concept
Memory Levels (Top to Bottom):
Two point eleven point two. Cache Memory and Locality of Reference
Locality of Reference Principle:
Two point eleven point three. Secondary Storage Devices
Four. Flash Drives and SD Cards:
Two point eleven point four. Virtual Memory
Two point twelve. Speed and Cost Trade-Offs
Two point twelve point one. Relationship between Speed, Cost, and Capacity There exists an inverse relationship among the three:
Two point twelve point two. Performance Optimization Techniques
· Overlaps stages of instruction execution to improve throughput
· Reduces access latency within rows
Effective memory system design aims to maximize performance within budget constraints. Strategies Include:
Two point thirteen. Summary
Two point fourteen Keywords
Two point fifteen Self-Assessment Questions
Two point sixteen Case Study